NXP Semiconductors /LPC800 /SPI0 /TXDATCTL

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Interpret as TXDATCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TXDAT0 (SSEL_ASSERTED_)TXSSELN 0RESERVED 0 (SSEL_NOT_DEASSERTED_)EOT 0 (DATA_NOT_EOF_THIS_P)EOF 0 (READ_RECEIVED_DATA_)RXIGNORE 0RESERVED 0FLEN0RESERVED

EOT=SSEL_NOT_DEASSERTED_, RXIGNORE=READ_RECEIVED_DATA_, EOF=DATA_NOT_EOF_THIS_P, TXSSELN=SSEL_ASSERTED_

Description

SPI Transmit Data with Control

Fields

TXDAT

Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.

TXSSELN

Transmit Slave Select . This field controls what is output for SSEL in master mode. The active state of the SSEL function is configured by bits in the CFG register.

0 (SSEL_ASSERTED_): SSEL asserted.

1 (SSEL_NOT_ASSERTED_): SSEL not asserted.

RESERVED

Reserved.

EOT

End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.

0 (SSEL_NOT_DEASSERTED_): SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.

1 (SSEL_DEASSERTED_THI): SSEL deasserted. This piece of data is treated as the end of a transfer. SSELs will be deasserted at the end of this piece of data.

EOF

End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.

0 (DATA_NOT_EOF_THIS_P): Data not EOF. This piece of data transmitted is not treated as the end of a frame.

1 (DATA_EOF_THIS_PIECE): Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.

RXIGNORE

Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process.

0 (READ_RECEIVED_DATA_): Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.

1 (IGNORE_RECEIVED_DATA): Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.

RESERVED

Reserved. Read value is undefined, only zero should be written.

FLEN

Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by multiple sequential frames Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 1 bit in length. 0x2 = Data frame is 3 bits in length. … 0xF = Data frame is 16 bits in length.

RESERVED

Reserved. Read value is undefined, only zero should be written.

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